M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 199

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

OR — Overrun Error Flag
NF — Noise Error Flag
FE — Framing Error Flag
PF — Parity Error Flag
14.2.3.5 SCI Status Register 2
Read: Anytime
Write: Has no meaning or effect
RAF — Receiver Active Flag
Freescale Semiconductor
New byte is ready to be transferred from the receive shift register to the receive data register and the
receive data register is already full (RDRF bit is set). Data transfer is inhibited until this bit is cleared.
Set during the same cycle as the RDRF bit but not set in the case of an overrun (OR).
Set when a 0 is detected where a stop bit was expected. Clear the FE flag by reading SC0SR1 with
FE set and then reading SC0DR.
Indicates if received data’s parity matches parity bit. This feature is active only when parity is enabled.
The type of parity tested for is determined by the PT (parity type) bit in SC0CR1.
This bit is controlled by the receiver front end. It is set during the RT1 time period of the start bit search.
It is cleared when an idle state is detected or when the receiver circuitry detects a false start bit
(generally due to noise or baud rate mismatch).
0 = No overrun
1 = Overrun detected
0 = Unanimous decision
1 = Noise on a valid start bit, any of the data bits, or on the stop bit
0 = Stop bit detected
1 = Zero detected rather than a stop bit
0 = Parity correct
1 = Incorrect parity detected
0 = Character is not being received.
1 = Character is being received.
Address:
Reset:
Read:
Write:
$00C5
Bit 7
0
0
Figure 14-8. SCI Status Register 2 (SC0SR2)
= Unimplemented
M68HC12B Family Data Sheet, Rev. 9.1
6
0
0
5
0
0
4
0
0
3
0
0
Serial Communication Interface (SCI)
2
0
0
1
0
0
Bit 0
RAF
0
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