M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 172

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

Enhanced Capture Timer (ECT) Module
PR2, PR1, and PR0 — Timer Prescaler Select Bits
13.4.9 Main Timer Interrupt Flag Registers
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be
C7F–C0F — Input Capture/Output Compare Channel n Flag
172
These three bits specify the number of ÷2 stages that are to be inserted between the module clock and
the main timer counter. See
next synchronized edge where all prescale counter stages equal 0.
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a 1
to the bit.
Use of the TFMOD bit in the input control system control register (ICSYS) register ($AB) in conjunction
with the use of the ICOVW register ($AA) allows a timer interrupt to be generated after capturing two
values in the capture and holding registers instead of generating an interrupt for every capture.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel ($90–$9F) will cause the corresponding channel flag CnF to be cleared. See
cleared). Writing a 0 will not affect current bit status.
Address: $008E
Reset:
Read:
Write:
Value
0
1
2
3
4
5
6
7
Bit 7
C7F
0
Figure 13-18. Main Timer Interrupt Flag 1 (TFLG1)
PR2
Table
0
0
0
0
1
1
1
1
C6F
6
0
M68HC12B Family Data Sheet, Rev. 9.1
Table 13-3. Prescaler Selection
13-3. The newly selected prescale factor will not take effect until the
PR1
0
0
1
1
0
0
1
1
C5F
5
0
PR0
C4F
0
1
0
1
0
1
0
1
4
0
C3F
3
0
Prescale Factor
C2F
2
0
128
16
32
64
1
2
4
8
C1F
1
0
Freescale Semiconductor
Bit 0
C0F
0
Figure
13-19.