M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 65

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M68HC12A4EVB

Manufacturer Part Number
M68HC12A4EVB
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of M68HC12A4EVB

Lead Free Status / Rohs Status
Not Compliant
Opcodes and Operands
3.7 Opcodes and Operands
The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing
mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing
capabilities.
Only 256 opcodes would be available if the range of values were restricted to the number that can be
represented by 8-bit binary numbers. To expand the number of opcodes, a second page is added to the
opcode map. Opcodes on the second page are preceded by an additional byte with the value $18.
To provide additional addressing flexibility, opcodes can also be followed by a postbyte or extension
bytes. Postbytes implement certain forms of indexed addressing, transfers, exchanges, and loop
primitives. Extension bytes contain additional program information such as addresses, offsets, and
immediate data.
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
65