M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 280

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

Analog-to-Digital Converter (ATD)
ADPU — ATD Disable Bit
AFFC — ATD Fast Flag Clear Bit
AWAI — ATD Stop in Wait Mode Bit
ASCIE — ATD Sequence Complete Interrupt Enable Bit
ASCIF — ATD Sequence Complete Interrupt Flag
17.3.4 ADT Control Register 3
Read: Anytime
Write: Anytime
The ATD control register 3 (ATDCTL3) is used to select the power-up mode, interrupt control, and freeze
control.
280
Software can disable the clock signal to the ATD and power down the analog circuits to reduce power
consumption. When reset to 0, the ADPU bit aborts any conversion sequence in progress. Because
the bias currents to the analog circuits are turned off, the ATD requires a period of recovery time to
stabilize the analog circuits after setting the ADPU bit.
Cannot be written in any mode.
0 = Disables the ATD, including the analog section for reduction in power consumption
1 = Allows the ATD to function normally
0 = ATD flag clearing operates normally (read the status register before reading the result register
1 = Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result
0 = ATD continues to run when the MCU is in wait mode.
1 = ATD stops to save power when the MCU is in wait mode.
0 = Disables ATD interrupt
1 = Enables ATD interrupt on sequence complete
0 = No ATD interrupt occurred
1 = ATD sequence complete
to clear the associated CCF bit).
register (ATD0–ATD7) will cause the associated CCF flag to clear automatically if it was set at
the time.
Address: $0063
Writing to this register aborts any current conversion sequence and
suspends module operation at breakpoint.
Reset:
Read:
Write:
Bit 7
0
0
Figure 17-5. ATD Control Register 3 (ATDCTL3)
= Unimplemented
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
5
0
0
NOTE
4
0
0
3
0
0
2
0
0
FRZ1
1
0
Freescale Semiconductor
FRZ0
Bit 0
0