EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 111
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
December 2010 Altera Corporation
Clock Regions
1
A spine clock is another layer of routing below the GCLKs, RCLKs, and PCLKs before
each clock is connected to the clock routing for each LAB row. The settings for spine
clocks are transparent to all users. The Quartus II software automatically routes the
spine clock based on the GCLK, RCLK, and PCLKs.
Arria II GX devices provide up to 64 distinct clock domains (16 GCLKs + 48 RCLKs)
in the entire device, while Arria II GZ devices provide up to 104 distinct clock
domains (16 GCLKs + 88 RCLKs). Use these clock resources to form the following
three types of clock regions:
■
■
■
To form the entire device clock region, a source (not necessarily a clock signal) drives a
GCLK network that can be routed through the entire device. This clock region has a
higher skew when compared with other clock regions, but allows the signal to reach
every destination in the device. This is a good option for routing global reset and clear
signals or routing clocks throughout the device.
To form a regional clock region, a source drives a single-quadrant of the device. This
clock region provides the lowest skew in a quadrant and is a good option if all
destinations are in a single device quadrant.
To form a dual-regional region, a single source (a clock pin or PLL output) generates a
dual-regional clock by driving two regional clock networks (one from each quadrant).
This technique allows destinations across two device quadrants to use the same
low-skew clock. The routing of this signal on an entire side has approximately the
same delay as in a regional clock region. Internal logic can also drive a dual-regional
clock network. For Arria II GX devices, corner PLL outputs generate a dual-regional
clock network through clock multiplexers that serve the two immediate quadrants of
the device. For Arria II GZ devices, corner PLL outputs only span one quadrant, they
cannot generate a dual-regional clock network.
Entire device
Regional
Dual regional
Arria II Device Handbook Volume 1: Device Interfaces and Integration
5–7
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