EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 492

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–2
Figure 2–1. Input Reference Clock Sources in a Transceiver Block
Note to
(1) One global clock line is available for each CMU PLL and receiver CDR in a transceiver block. This configuration allows each CMU PLL and receiver
Arria II Device Handbook Volume 2: Transceivers
CDR to derive its input reference clock from a separate FPGA CLK input pin.
refclk0
refclk1
Figure
2–1:
/2
/2
Figure 2–1
within a transceiver block.
shows the input reference clock sources for CMU PLLs and receiver CDRs
Global Clock Line (1)
Global Clock Line (1)
Global Clock Line (1)
Global Clock Line (1)
Global Clock Line (1)
Global Clock Line (1)
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
6
6
6
6
6
6
CMU PLL and Receiver CDR Input Reference Clocking
Chapter 2: Transceiver Clocking in Arria II Devices
CMU1 PLL
CMU0 PLL
CDR
CDR
CDR
CDR
December 2010 Altera Corporation
Transceiver Block
CMU1 Block
CMU0 Block
Channel 3
Channel 2
Channel 1
Channel 0