EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 528

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–38
Figure 2–22. Sixteen Identical Channels Across Four Transceiver Blocks for Example 4
Arria II Device Handbook Volume 2: Transceivers
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Common Clock Driver Selection Rules
The common clock driver driving the tx_coreclk ports of all identical channels must
have 0 PPM frequency difference with respect to the transmitter phase compensation
FIFO read clocks of these channels. If there is any frequency difference between the
FIFO write clock (tx_coreclk) and the FIFO read clock, the FIFO overflows or under
runs, resulting in corrupted data transfer between the FPGA fabric and the
transmitter.
Figure 2–22
transceiver blocks. The tx_coreclk ports of all 16 transmitter channels are
connected together and driven by a common clock driver. This common clock
driver also drives the transmitter data and control logic of all 16 transmitter
channels in the FPGA fabric. Only one global or regional clock resource is used
with this clocking scheme, compared with four clock resources (global, regional,
or both) needed without the tx_coreclk ports (the Quartus II software-selected
transmitter phase compensation FIFO write clock).
Example 4: Sixteen Identical Channels Across Four Transceiver Blocks
shows 16 identical transmitter channels located across four
tx_clkout[15:12]
tx_clkout[11:8]
tx_clkout[7:4]
tx_clkout[3:0]
Common Clock Driver
tx_coreclk[15:12]
tx_coreclk[11:8]
tx_coreclk[7:4]
tx_coreclk[3:0]
FPGA Fabric
Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Channel [15:12]
Channel [11:8]
Channel [3:0]
Channel [7:4]
and Control
and Control
and Control
and Control
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
December 2010 Altera Corporation