EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 542
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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2–52
Arria II Device Handbook Volume 2: Transceivers
Figure 2–29. Sixteen Identical Channels Across Four Transceiver Blocks for Example 9
Common Clock Driver Selection Rules
The common clock driver driving the rx_coreclk ports of all channels must have a
0 PPM frequency difference with respect to the receiver phase compensation FIFO
write clocks of these channels. If there is any frequency difference between the FIFO
read clock (rx_coreclk) and the FIFO write clock, the FIFO overflows or under runs,
resulting in corrupted data transfer between the FPGA fabric and the receiver.
Figure 2–29
incoming serial data to all 16 channels has a 0 PPM frequency difference with
respect to each other. The rx_coreclk ports of all 16 channels are connected
together and driven by a common clock driver. This common clock driver also
latches the receiver data and status logic of all 16 receiver channels in the FPGA
fabric. Only one clock resource (global, regional, or both) is used with this clocking
scheme, compared with 16 clock resources (global, regional, or both) needed
without the rx_coreclk ports (the Quartus II software-selected receiver phase
compensation FIFO read clock).
Example 9: Sixteen Identical Channels Across Four Transceiver Blocks
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
shows 16 channels located across four transceiver blocks. The
rx_clkout[15:12]
rx_clkout[11:8]
rx_clkout[7:4]
rx_clkout[3:0]
Common Clock Driver
rx_coreclk[15:12]
Chapter 2: Transceiver Clocking in Arria II Devices
rx_coreclk[11:8]
rx_coreclk[7:4]
rx_coreclk[3:0]
FPGA Fabric-Transceiver Interface Clocking
FPGA Fabric
December 2010 Altera Corporation
Channel [15:12]
Channel [11:8]
Channel [3:0]
Channel [7:4]
and Status
and Status
and Status
and Status
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
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