EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 392

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EP2AGX45DF29I5

Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX45DF29I5

Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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1–6
Clock Multiplier Units (CMU)
Arria II Device Handbook Volume 2: Transceivers
1
Each transceiver block contains two CMU blocks, which contain a CMU phase-locked
loop (PLL) that provides clocks to all the transmitter channels in the same transceiver
block. These two CMU blocks can provide two independent high-speed clocks per
transceiver block.
The CMU PLL is also known as the TX PLL.
The CMU PLLs in CMU0 and CMU1 are identical and each transmitter channel in the
transceiver block can receive a high-speed clock from either of the two CMU PLLs.
However, the CMU0 block has an additional clock divider after the CMU0 PLL to support
bonded functional modes where multiple channels share a common clock to reduce
skew between the channels. With the ALTGX MegaWizard Plug-In Manager, you can
select the bonded functional modes used in ×4 Basic, PCIe, and XAUI.
Chapter 1: Transceiver Architecture in Arria II Devices
December 2010 Altera Corporation
Clock Multiplier Units (CMU)

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