EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 585
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 4: Reset Control and Power Down in Arria II Devices
Transceiver Reset Sequences
Figure 4–6. Sample Reset Sequence of Receiver-Only Channel—Receiver CDR in Automatic Lock Mode
December 2010 Altera Corporation
Reset Signals
Output Status Signals
rx_analogreset
rx_digitalreset
rx_freqlocked
Transmitter Only Channel
This configuration contains only a transmitter channel. If you create a Transmitter
Only instance in the ALTGX MegaWizard Plug-In Manager, use the same reset
sequence as shown in
Receiver Only Channel—Receiver CDR in Automatic Lock Mode
This configuration contains only a receiver channel. If you create a Receiver Only
instance in the ALTGX MegaWizard Plug-In Manager with the receiver CDR in
automatic lock mode, use the reset sequence shown in
As shown in
CDR in automatic lock mode configuration:
1. After power up, wait for the busy signal to be de-asserted (marker 1).
2. De-assert the rx_analogreset signal (marker 2).
3. Keep the rx_digitalreset signal asserted during this time period. After you
4. Wait for the rx_freqlocked signal to go high (marker 3).
5. After rx_freqlocked goes high, wait at least 4 s and then de-assert the
busy
de-assert the rx_analogreset signal, the receiver PLL starts locking to the receiver
input reference clock.
rx_digitalreset signal (marker 4). At this point, the receiver is ready to receive
data.
Figure
Two parallel clock cycles
1
4–6, perform the following reset sequence steps for the receiver
Figure 4–2 on page
2
4–5.
3
4 μs
Arria II Device Handbook Volume 2: Transceivers
4
Figure
4–6.
4–11
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