EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 243

no-image

EP2AGX45DF29I5

Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX45DF29I5

Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX45DF29I5
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2AGX45DF29I5
Manufacturer:
ALTERA
0
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP2AGX45DF29I5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
0
Part Number:
EP2AGX45DF29I5N
0
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Locations of the I/O Banks
Locations of the I/O Banks
Figure 8–1. High-Speed Differential I/Os with DPA Block Locations in an Arria II GX Device
Notes to
(1) This figure is a top view of the silicon die, which corresponds to a reverse view for flip chip packages. It is a graphical representation only.
(2) Applicable to EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(3) There are no center PLLs on the right I/O banks for EP2AGX45 and EP2AGX65 devices.
December 2010 Altera Corporation
Figure
8–1:
Transceiver
Blocks
PLL
PLL
Arria II I/Os are divided into 16 to 20 I/O banks. For Arria II GX devices, the
high-speed differential I/O s are located at the right side of the device. For Arria II GZ
devices, the high-speed differential I/Os are located at the right and left sides of the
device.
Figure 8–1
and
High-Speed Differential I/O,
High-Speed Differential I/O,
and Memory Interface
General Purpose I/O,
and Memory Interface
General Purpose I/O,
Figure 8–2
Embedded Memory, and Clock Networks)
(Logic Elements, DSP,
show a high-level chip overview of Arria II devices.
FPGA Fabric
Arria II Device Handbook Volume 1: Device Interfaces and Integration
High-Speed Differential I/O,
High-Speed Differential I/O,
and Memory Interface
General Purpose I/O,
and Memory Interface
General Purpose I/O,
(Note
I/O with DPA,
I/O with DPA,
High-Speed
High-Speed
Differential
Differential
Purpose
Purpose
I/O, and
Memory
Interface
I/O, and
Memory
Interface
General
General
PLL
PLL
PLL
PLL
1), (2),
(3)
8–3

Related parts for EP2AGX45DF29I5