EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 592

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

4–18
Figure 4–12. Reset Sequence in Basic ×1 Mode with Receiver CDR in Automatic Lock Mode (Channel and TX PLL
select/reconfig Option)
Arria II Device Handbook Volume 2: Transceivers
Reset Sequence with the Channel and TX PLL Select/Reconfig Option
Reset and Control Signals
Output Status Signals
Use the example reset sequence shown in
dynamic reconfiguration controller to change the TX PLL settings of the transceiver
channel. In this example, the dynamic reconfiguration is used to dynamically
reconfigure the data rate of the transceiver channel configured in Basic ×1 mode with
the receiver CDR in automatic lock mode.
As shown in
dynamic reconfiguration controller to change the configuration of the transceiver
channel:
1. After power up and establishing that the transceiver is operating correctly, write
2. Assert the tx_digitalreset, rx_analogreset, and rx_digitalreset signals.
3. As soon as write_all is asserted, the dynamic reconfiguration controller starts to
4. Wait for the assertion of the channel_reconfig_done signal (marker 4), which
reconfig_mode_sel[2:0]
channel_reconfig_done
the new value in the appropriate registers (including reconfig_mode_sel[2:0])
and subsequently assert the write_all signal (marker 1) to initiate the dynamic
reconfiguration.
f
execute its operation, as indicated by the assertion of the busy signal (marker 2).
indicates the completion of dynamic reconfiguration in this mode.
rx_analogreset
rx_digitalreset
tx_digitalreset
rx_reqlocked
For more information, refer to
Reconfiguration in Arria II
write_all
Figure
busy
4–12, perform the following reset procedure when using the
New Value
1
1
1
2
Devices.
3
Chapter 4: Reset Control and Power Down in Arria II Devices
AN 558: Implementing Dynamic
4
Figure 4–12
five parallel clock cycles
5
6
7
4 μs
8
when you are using the
Dynamic Reconfiguration Reset Sequences
December 2010 Altera Corporation