EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 508
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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2–18
Arria II Device Handbook Volume 2: Transceivers
Receiver Channel Datapath Clocking
f
This section describes receiver PMA and PCS datapath clocking in supported
configurations. The receiver datapath clocking varies between non-bonded and
bonded channel configurations. It also varies with the use of PCS blocks; for example,
deskew FIFO and rate matcher.
Non-Bonded Channel Configurations
In non-bonded channel configurations, the receiver PCS blocks of each channel are
clocked independently. Each non-bonded channel also has separate rx_analogreset
and rx_digitalreset signals that allow independent reset of the receiver PCS logic in
each channel.
For more information about transceiver reset and power-down signals, refer to the
Reset Control and Power Down in Arria II Devices
In addition, using the rate matcher block affects PCS clocking in non-bonded channel
configurations.
Non-Bonded Receiver Clocking Without Rate Matcher
The following functional modes have non-bonded receiver channel configuration
without rate-matcher:
■
■
■
■
■
Serial RapidIO
SONET/SDH
SDI
CPRI/OBSAI
Basic without rate matcher
chapter.
Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
December 2010 Altera Corporation
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