EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 537
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
1
Bonded Channel Configuration
All bonded transceiver channel configurations have a rate matcher in the receiver
data path.
In the ×4 bonded channel configurations, the Quartus II software automatically drives
the read port of the receiver phase compensation FIFO in all four channels with the
coreclkout signal. Use the coreclkout signal to latch the receiver data and status
signals from all four channels in the FPGA fabric.
In ×8 bonded channel configurations, the Quartus II software automatically drives the
read port of the receiver phase compensation FIFO in all eight channels with the
coreclkout signal from the master transceiver block. Use the coreclkout signal to
latch the receiver data and status signals from all eight channels in the FPGA fabric.
This configuration uses one FPGA global or regional clock resource per bonded link
for the coreclkout signal.
Arria II Device Handbook Volume 2: Transceivers
2–47
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