EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 69
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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EP2AGX45DF29I5N
Manufacturer:
ALTERA
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201
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EP2AGX45DF29I5N
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Chapter 3: Memory Blocks in Arria II Devices
Design Considerations
Figure 3–23. MLABs Mixed-Port Read-During-Write: Old Data Mode
Figure 3–24. MLABs Mixed-Port Read-During-Write: Don’t Care Mode
December 2010 Altera Corporation
q_b(registered)
q_b(registered)
1
byteena_a
wraddress
rdaddress
byteena_a
wraddress
rdaddress
data_in
wrena
data_in
clk_a
wrena
clk_a
Read-during-write behavior is controlled using the RAM MegaWizard Plug-In
Manager. For more information about how to implement the desired behavior, refer to
the
Figure 3–23
behavior for old data mode in MLABs.
Figure 3–24
behavior for don’t care mode in MLABs.
Internal Memory (RAM and ROM) Megafunction User
AAAA
shows a sample functional waveform of mixed-port read-during-write
shows a sample functional waveform of mixed-port read-during-write
AAAA
11
11
A0 (old data)
A0
A0
A0
A0
AAAA
BBBB
01
BBBB
01
AAAA
AABB
CCCC
10
CCCC
10
Arria II Device Handbook Volume 1: Device Interfaces and Integration
AABB
DDDD
DDDD
CCBB
11
11
A1(old data)
DDDD
EEEE
A1
A1
EEEE
A1
A1
01
01
Guide.
DDDD
FFFF
DDEE
FFFF
10
10
DDEE
FFEE
3–23
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