EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 93
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Figure 4–14. Loopback Mode for Half-DSP Block
Note to
(1) Block output for accumulator overflow and saturate overflow.
December 2010 Altera Corporation
Figure
dataa_0[17..0]
datab_0[17..0]
dataa_1[17..0]
datab_1[17..0]
4–14:
1
1
zero_loopback
At compile time, you must select the option to use the loopback mode or the general
two-multiplier adder mode.
If all the inputs are full 18 bits and unsigned, the result requires 37 bits for
two-muliplier adder mode. Because the output data width in two-multiplier adder
mode is limited to 36 bits, this 37-bit output requirement is not allowed. Any other
combination that does not violate the 36-bit maximum result is permitted; for
example, two 16 × 16 signed two-multiplier adders is valid.
Two-multiplier adder mode supports the rounding and saturation logic unit. You can
use pipeline registers and output registers in the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
Half-DSP Block
loopback
clock[3..0]
ena[3..0]
aclr[3..0]
output_saturate
output_round
+
Arria II Device Handbook Volume 1: Device Interfaces and Integration
signa
signb
overflow (1)
result[ ]
4–21
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