EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 496
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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2–6
Transceiver Channel Datapath Clocking
Arria II Device Handbook Volume 2: Transceivers
Transmitter Channel Datapath Clocking
f
Dedicated CLK Input Pins on the FPGA Global Clock Network
Arria II GX and GZ devices provide six differential CLK[5:0] input pins located in
non-transceiver I/O banks that you can use to provide the input reference clock to the
transceiver blocks. The Quartus II software automatically chooses the global clock
network to route the input reference clock signal from the CLK pins to the transceiver
blocks.
For more information, refer to the “Dedicated Clock Input Pins” section in the
Networks and PLLs in Arria II Devices
One global clock resource is available for each CMU PLL and receiver CDR within a
transceiver block. This configuration allows each CMU PLL and receiver CDR to
derive its input reference clock from a separate FPGA CLK input pin.
Clock Output from Left and Right PLLs in the FPGA Fabric
You can use the synthesized clock output from one of the left or right PLLs to provide
the input reference clock to the CMU PLLs and receiver CDRs. Arria II GX devices
provide a dedicated clock path from the left PLLs (PLL_L1, PLL_L2, PLL_L3, and
PLL_L4) in the FPGA fabric to the PLL cascade network located on the left side of the
device.
Arria II GZ devices also provide a dedicated clock path from the right PLLs (PLL_R1,
PLL_R2, PLL_R3, and PLL_R4) in the FPGA fabric to the PLL cascade network located
on the right side of the device. The additional clock multiplication factors available in
the left and right PLLs allow more options for on-board crystal oscillator frequencies.
For more information, refer to
page
The following sections describe transmitter and receiver channel datapath clocking in
various configurations. Datapath clocking varies with physical coding sublayer (PCS)
configurations in different functional modes and channel bonding options.
This section describes transmitter channel PMA and PCS datapath clocking in
non-bonded and bonded channel configurations. Transmitter datapath clocking in
bonded channel configurations provide low channel-to-channel skew when
compared with non-bonded channel configurations.
The following factors contribute to transmitter channel-to-channel skew:
■
■
High-speed serial clock and low-speed parallel clock skew between channels
Unequal latency in the transmitter phase compensation FIFO
2–56.
“FPGA Fabric PLL-Transceiver PLL Cascading” on
chapter.
Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
December 2010 Altera Corporation
Clock
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