EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 470
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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EP2AGX45DF29I5N
Manufacturer:
ALTERA
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EP2AGX45DF29I5N
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1–84
Arria II Device Handbook Volume 2: Transceivers
c
Figure 1–79
columns must be deleted.
Figure 1–79. Example of Rate Match Deletion in XAUI Mode
Figure 1–80
columns must be inserted.
Figure 1–80. Example of Rate Match Insertion in XAUI Mode
The rate match FIFO does not insert or delete code groups automatically to overcome
FIFO empty or full conditions. In this case, the rate match FIFO asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least three recovered clock cycles to
indicate rate match FIFO full and empty conditions, respectively. You must then assert
the rx_digitalreset signal to reset the receiver PCS blocks.
rx_rmfifodatadeleted
rx_rmfifodatainserted
shows an example of rate match deletion in the case where three ||R||
shows an example of rate match insertion in the case where two ||R||
dataout[3]
dataout[2]
dataout[1]
dataout[0]
datain[3]
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datain[1]
datain[0]
dataout[3]
dataout[2]
dataout[1]
dataout[0]
datain[3]
datain[2]
datain[1]
datain[0]
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First
||R||
Chapter 1: Transceiver Architecture in Arria II Devices
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December 2010 Altera Corporation
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Functional Modes
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