EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 513
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
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Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
Figure 2–15. Receiver Datapath Clocking in ×4 Bonded Channel Configuration with Deskew FIFO
December 2010 Altera Corporation
Fabric
FPGA
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
coreclkout
×4 Bonded Channel Configuration with Deskew FIFO
XAUI functional mode has ×4 bonded channel configuration with deskew FIFO.
Figure 2–15
with deskew FIFO.
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
Channel 3
Channel 2
Channel 1
Channel 0
shows receiver datapath clocking in ×4 channel bonding configurations
Input Reference Clock
Input Reference Clock
/2
/2
/2
/2
/2
CMU1_PLL
CMU0_PLL
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
CMU1 Clock Divider
CMU0 Clock Divider
Arria II Device Handbook Volume 2: Transceivers
CMU1_Channel
CMU0_Channel
Ch3
Ch2
Ch1
Low-Speed Parallel Clock from CMU0 Clock Divider
FPGA Fabric-Transceiver Interface Clock
Serial Recovered Clock
Ch0 Parallel Recovered Clock
Receiver Channel
Receiver Channel
Receiver Channel
Receiver Channel
PMA
PMA
PMA
PMA
Reference
Reference
Reference
Reference
Clock
Clock
Clock
Clock
Input
Input
Input
Input
2–23
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