EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 144

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–40
Figure 5–33. Manual Clock Switchover Circuitry in PLLs for Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
f
clkswitch
inclk0
inclk1
Manual Clock Switchover Mode
In manual clock switchover mode, the clkswitch signal controls whether inclk0 or
inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected. A
low-to-high transition on clkswitch and being held high for at least three inclk cycles
begins a clock switchover event. You must bring the clkswitch signal back low again
to perform another switchover event in the future. If you do not require another
switchover event in the future, you can leave clkswitch in a logic high state after the
initial switch. Pulsing clkswitch high for at least three inclk cycles performs another
switchover event. If inclk0 and inclk1 are different frequencies and are always
running, the clkswitch minimum high time must be greater than or equal to three of
the slower frequency inclk0 and inclk1 cycles.
Figure 5–33
For more information about PLL software support in the Quartus II software, refer to
the
Clock Switchover Guidelines
Use the following guidelines when implementing clock switchover in Arria II PLLs.
■
■
■
Automatic clock switchover requires that the inclk0 and inclk1 frequencies be in
100% (2×) of each other. Failing to meet this requirement causes the clkbad[0] and
clkbad[1] signals to not function properly.
When you use manual clock switchover mode, the difference between inclk0 and
inclk1 can be more than 100% (2×). However, differences in frequency, or phase of
the two clock sources, or both, are likely to cause the PLL to lose lock. Resetting the
PLL ensures that the correct phase relationships are maintained between the input
and output clocks.
1
Applications that require a clock switchover feature and a small frequency drift
must use a low-bandwidth PLL. The low-bandwidth PLL reacts more slowly than
the high-bandwidth PLL to reference the input clock changes. When the
switchover event occurs, a low-bandwidth PLL propagates the stopping of the
clock to the output more slowly than the high-bandwidth PLL. However, be aware
that the low-bandwidth PLL also increases lock time.
Phase-Locked Loops (ALTPLL) Megafunction User
Control Logic
Clock Switch
Both inclk0 and inclk1 must be running when the clkswitch signal goes
high to start the manual clock switchover event. Failing to meet this
requirement causes the clock switchover to not function properly.
shows a block diagram of the manual switchover circuit.
muxout
n Counter
refclk
Chapter 5: Clock Networks and PLLs in Arria II Devices
Guide.
PFD
December 2010 Altera Corporation
fbclk
PLLs in Arria II Devices