EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 405

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Arria II Devices
Transmitter Channel Datapath
Figure 1–21. Serializer Bit Order
Note to
(1) The input data to the serializer is 8 bits (channel width = 8 bits with the 8B/10B encoder disabled).
December 2010 Altera Corporation
Low-Speed Parallel Clock
High-Speed Serial Clock
Figure
tx_datain[7:0]
tx_dataout[0]
1–21:
Serializer
The serializer converts the incoming low-speed parallel signal from the transceiver
PCS to the high-speed serial data and sends its LSB first to the transmitter output
buffer.
interface.
Figure 1–20. Serializer Block in an 8-Bit PCS-PMA Interface
Note to
(1) This clock is provided by the CMU0 clock divider of the master transceiver block and is only used in ×8 mode.
Figure 1–21
Parallel Clock from Master Transceiver Block (1)
00000000
Serial Clock from Master Transceiver Block (1)
Parallel Clock from CMU0 Clock Divider
Figure
Parallel Clock from Local Divider Block
Figure 1–20
Serial Clock from CMU0 Clock Divider
Serial Clock from Local Divider Block
(Note 1)
1–20:
shows an example of serialized data with a 8'b01101010 value.
Data from the PCS Block
shows the serializer block diagram in an 8-bit PCS-to-PMA
01101010
0
1
0
1
0
1
8
1
Parallel Clock
0
Low-Speed
High-Speed
Serial Clock
Arria II Device Handbook Volume 2: Transceivers
D7
D6
D5
D4
D3
D2
D1
D0
00000000
D7
D6
D5
D4
D3
D2
D1
D0
To Output Buffer
1–19