EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 147

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–36. PLL Reconfiguration Waveform for Arria II Devices
December 2010 Altera Corporation
CONFIGUPDATE
SCANDATAOUT
SCANCLKENA
SCANDONE
SCANDATA
SCANCLK
ARESET
f
1
For more information about the PLL reconfiguration port signals, refer to the
Locked-Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User
The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, all counters are not simultaneously updated.
To reconfigure the PLL counters, follow these steps:
1. Assert the SCANCLKENA signal at least one SCANCLK cycle prior to shifting in the first
2. Serial data (SCANDATA) is shifted into the scan chain on the second rising edge of
3. For Arria II GX devices, after all 180 bits are scanned into the scan chain, the
4. The CONFIGUPDATE signal is asserted for one SCANCLK cycle to update the PLL
5. The SCANDONE signal goes high indicating the PLL is being reconfigured. A falling
6. Reset the PLL with the ARESET signal if you make any changes to the M, N, or
7. Repeat steps
Figure 5–36
Dn_old
bit of SCANDATA (Dn [Arria II GX devices]) or D0 [Arria II GZ devices).
SCANCLK.
SCANCLKENA signal is deasserted to prevent inadvertent shifting of bits in the scan
chain. For Arria II GZ devices, after all 234 bits (top and bottom PLLs) or 180 bits
(left and right PLLs) have been scanned into the scan chain, the SCANCLKENA signal
is deasserted to prevent inadvertent shifting of bits in the scan chain.
counters with the contents of the scan chain.
edge indicates the PLL counters are updated with new settings.
post-scale output C counters or the Icp, R, or C settings.
Dn
shows a functional simulation of the PLL reconfiguration feature.
1
through
5
to reconfigure the PLL any number of times.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
D0_old
D0
Dn
Guide.
Phase
5–43