EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 593
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 4: Reset Control and Power Down in Arria II Devices
Power Down
Power Down
Figure 4–13. Sample Reset Sequence of Four Receiver and Transmitter Channels—Receiver CDR in Automatic Lock
Mode with Optional gxb_powerdown Signal
December 2010 Altera Corporation
Reset/Power Down Signals
Output Status Signals
gxb_powerdown
pll_powerdown
rx_analogreset
tx_digitalreset
rx_digitalreset
rx_freqlocked
pll_locked
busy
5. After assertion of the channel_reconfig_done signal, de-assert tx_digitalreset
6. Finally, wait for the rx_freqlocked signal to go high. After rx_freqlocked goes
The Quartus II software automatically selects the power down channel feature, which
takes effect when you configure the Arria II GX or GZ device. All unused transceiver
channels and blocks are powered down to reduce overall power consumption.
The gxb_powerdown signal is an optional transceiver block signal. It powers down all
the blocks in the transceiver block. The minimum pulse width for this signal is 1 s.
After power up, if you use the gxb_powerdown signal, wait for de-assertion of the busy
signal, then assert the gxb_powerdown signal for a minimum of 1 s. To finish, follow
the sequence shown in
(marker 5) and wait for at least five parallel clock cycles to de-assert the
rx_analogreset signal (marker 6).
high (marker 7), wait for 4 s to de-assert the rx_digitalreset signal (marker 8).
At this point, the receiver is ready for data traffic.
Figure
2
1
4–13.
1 μs
3
4
5
6
Arria II Device Handbook Volume 2: Transceivers
7
4 μs
8
4–19
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