EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 233
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
December 2010 Altera Corporation
Arria II GZ Dynamic On-Chip Termination Control
I/O Element Registers
f
Figure 7–24
required to dynamically turn on the on-chip parallel termination (R
read and turn R
For more information about the dynamic OCT control block, refer to the
in Arria II Devices
Figure 7–24. Dynamic OCT Control Block for Arria II GZ Devices
Note to
(1) The write clock comes from the PLL.
IOE registers are expanded to allow source-synchronous systems to have faster
register-to-register transfers and resynchronization. For Arria II GX devices, both top,
bottom, and right IOEs have the same capability. Right IOEs have extra features to
support LVDS data transfer. For Arria II GZ devices, both top and bottom, and left
and right IOEs have the same capability. Left and right IOEs have extra features to
support LVDS data transfer.
Figure
7–24:
shows the dynamic OCT control block. The block includes all the registers
T
OCT off during a write.
chapter.
OCT Control Path
Half-Rate Clock
OCT Control
OCT
2
Arria II Device Handbook Volume 1: Device Interfaces and Integration
HDR
Block
DFF
Write Clock (1)
Resynchronization
Registers
DFF
OCT Enable
T
OCT) during a
I/O Features
7–37
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