EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 156
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
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Price
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Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
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5–52
Document Revision History
Table 5–23. Document Revision History
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
July 2010
November 2009
June 2009
February 2009
Date
PLL Specifications
f
Version
For more information about PLL timing specifications, refer to the
Arria II
Table 5–23
4.0
2.0
3.0
1.1
1.0
■
■
■
■
■
■
■
Updated for Arria II GX v10.0 release:
■
■
■
■
Updated for Arria II GX v9.1 release:
■
■
■
■
■
■
■
Initial release
Devices.
Updated for the Quartus II software version 10.1 release.
Added Arria II GZ devices information.
Updated
Added
Figure
Figure
Added
Added
Minor text edit.
Updated “Clock Regions” and “Arria II PLL Hardware Overview” sections.
Updated Figure 5–44.
Removed sub-regional clock references.
Minor text edit.
Updated Table 5–1.
Updated Figure 5–14.
Updated the “Periphery Clock (PCLK) Networks” and “Cascading PLLs” sections.
Minor text edit.
Updated Table 5–8.
Updated Figure 5–13 and Figure 5–14.
Updated the “PLL Clock I/O Pins” and “PLL Reconfiguration Hardware Implementation”
sections.
shows the revision history for this document.
5–11,
5–27,
Figure
Table
“Clock Sources Per Quadrant”
Table
5–5,
Figure
Figure
5–2,
5–1,
Table
Figure
Table
5–16,
5–38, and
5–7,
5–12,
5–3,
Figure
Table
Figure
Figure
Table
5–18,
5–9,
5–39.
5–4,
5–20, and
and
Changes
Figure
Table
Chapter 5: Clock Networks and PLLs in Arria II Devices
“External Feedback Mode”
Figure
5–11,
5–19,
Table
5–5,
andTable
Figure
5–21.
Figure
December 2010 Altera Corporation
5–24,
5–16.
5–7,
Figure
Figure
Document Revision History
Device Datasheet for
sections.
5–26,
5–15,
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