MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 121
MC68EN360ZQ25VL
Manufacturer Part Number
MC68EN360ZQ25VL
Description
IC MPU QUICC 32BIT 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360ZQ25VL.pdf
(962 pages)
Specifications of MC68EN360ZQ25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360ZQ25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360ZQ25VL PDF datasheet #4
- Current page: 121 of 962
- Download datasheet (4Mb)
The QUICC retries any read or write cycle of a read-modify-write operation separately; RMC
remains asserted during the entire retry sequence.
Asserting BR at the same time as BERR and HALT provides a relinquish and retry opera-
tion. The QUICC does not relinquish the bus during a read-modify-write cycle, but may relin-
quish the bus between any other bus cycles. (i.e. relinquish-and-retry has priority over bus
coherency, except in the case of read-modify-write cycles). Any device that requires the
QUICC to give up the bus and retry a bus cycle during a read-modify-write cycle must assert
BERR and BR only (HALT must not be included). The bus error handler software should
examine the read-modify-write bit in the special status word (refer to Section 5 CPU32+) and
take the appropriate action to resolve this type of fault when it occurs.
FC3–FC0
DSACKx
A31–A0
D31–D0
CLKO1
BERR
HALT
R/W
AS
DS
When the relinquish and retry is asserted during an internal mas-
ter's word access to an 8-bit port, and the external master that
takes the bus performs an external-to-internal bus cycle, the en-
S0
Freescale Semiconductor, Inc.
S2
For More Information On This Product,
READ CYCLE WITH
Figure 4-31. Retry Sequence
SW
RETRY
MC68360 USER’S MANUAL
Go to: www.freescale.com
IGNORED
SW
DATA
NOTE
S4
HALT
S0
READ RERUN
S2
S4
Bus Operation
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