MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 350

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

IDMA Channels
7.6.2 IDMA Registers
Each IDMA channel has eight registers that define its specific operation. These registers
include a 32-bit source address pointer register (SAPR), a 32-bit destination address pointer
register (DAPR), an 8-bit function code register (FCR), a 32-bit byte count register (BCR), a
16-bit channel mode register (CMR), an 16-bit channel configuration register (ICCR), an 8-
bit channel status register (CSR), and an 8-bit channel mask register (CMAR). These regis-
ters provide the addresses, transfer count, and configuration information necessary to set
up a transfer. They also provide a means of controlling the IDMA channel and monitoring its
status. All registers can be modified by the CPU32+ core.
For the auto buffer and buffer chaining modes, the RISC controller uses a buffer descriptor
ring to automatically initialize the DAPR, SAPR, and BCR. The buffer descriptor ring resides
in dual-port RAM so that it may be accessed by the RISC controller without bus overhead.
The IDMA channel also includes a 32-bit data holding register (DHR), which is not accessi-
ble to the CPU32+ core and is used by the IDMA for temporary data storage.
7.6.2.1 IDMA CHANNEL CONFIGURATION REGISTER (ICCR). The 16-bit ICCR config-
ures both IDMA channels. It is always readable and writable in the supervisor mode,
although writing is not recommended unless the module is disabled. It is initialized to $0000
at reset.
STP—Stop Bit
7-26
STP
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• Up to 50 Mbyte/sec Transfer Rates in Single Address Mode and 25 Mbyte/sec in Dual
• 32-Bit Byte Transfer Counters
• 32-Bit Address Pointers That Can Increment or Remain Constant
• Operand Packing and Unpacking for Dual Address Transfers using the Most Efficient
• Supports All Bus-Termination Modes
• Provides Full DMA Handshake for Cycle Steal and Burst Transfers
• Supports Fixed and Rotating Priority Between IDMA Channels
• Buffer Handling Modes: Single Buffer, Auto Buffer, and Buffer Chaining
Address Mode (assuming a 25-MHz system clock)
Techniques
0 = The system clock operates normally within the IDMA.
1 = Stop the system clock to the IDMA channels. This setting is used to conserve pow-
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er when both IDMAs are unused.
FRZ
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ARBP
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Freescale Semiconductor, Inc.
For More Information On This Product,
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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