MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 562
MC68EN360ZQ25VL
Manufacturer Part Number
MC68EN360ZQ25VL
Description
IC MPU QUICC 32BIT 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360ZQ25VL.pdf
(962 pages)
Specifications of MC68EN360ZQ25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360ZQ25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360ZQ25VL PDF datasheet #4
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- Download datasheet (4Mb)
Serial Communication Controllers (SCCs)
7.10.23.3 LEARNING ETHERNET ON THE QUICC. The following paragraphs detail the
Ethernet functionality on the QUICC. However, they show the additions made to the stan-
dard SCC functionality to implement Ethernet. Therefore, the reader is encouraged to learn
the basics of the SCCs and the overall architecture of the CPM before attempting to learn
this section in great detail.
A first-time user of the QUICC who plans to use Ethernet on the QUICC should first read the
following sections of this user manual.
7-238
• External CAM Support on Both Serial and System Bus Interfaces
• Up to Eight Parallel I/O Pins May Be Sampled and Appended to Any Frame
• Heartbeat Indication
• Transmitter Network Management and Diagnostics
• Receiver Network Management and Diagnostics
• Error Counters
• Internal and External Loopback Mode
1. 7.1 RISC Controller, 7.2 Command Set, and 7.3 Dual-Port RAM. The RISC controller
2. 7.7 SDMA Channels discusses how SDMA channels are used to transfer data to/from
3. 7.8.9 NMSI Configuration explains how clocks are routed to the SCCs through the
4. 7.10.1 SCC Overview contains more detailed information on the SCCs that are appli-
—Physical—One 48-Bit Address Recognized or 64-Bin Hash Table for Physical Ad-
—Logical—64-Bin Group Address Hash Table plus Broadcast Address Checking
—Promiscuous—Receives All Addresses, but Discards Frame If Reject Pin Asserted
—Lost Carrier Sense
—Underrun
—Number of Collisions Exceeded the Maximum Allowed
—Number of Retries per Frame
—Deferred Frame Indication
—Late Collision
—CRC Error Indication
—Nonoctet Alignment Error
—Frame Too Short
—Frame Too Long
—Overrun
—Busy (Out of Buffers)
—Discarded Frames (Out of Buffers or Overrun Occurred)
—CRC Errors
—Alignment Errors
is used to issue special commands to the Ethernet channel. The dual-port RAM is
used to load Ethernet parameters and initialize BDs for use by the Ethernet channel.
the Ethernet channel and system memory.
bank of clocks.
dresses
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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