MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 498

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Serial Communication Controllers (SCCs)
occur; a zero represents a masked bit position. Upon an address match, the address and
the data following are written into the data buffers. When the addresses are not matched
and the frame is error-free, the nonmatching address received counter (NMARC) is incre-
mented.
RFTHR. The received frames threshold value is used to reduce the interrupt overhead that
might otherwise occur when a series of short HDLC frames arrives, each causing an RXF
interrupt. By setting the RFTHR value, the user can limit the frequency of RXF interrupts.
The RXF interrupt will only occur when the RFTHR value is reached. RFCNT is a down-
counter used to implement this feature.
7.10.17.5 HDLC PROGRAMMING MODEL. The CPU32+ core configures each SCC to
operate in one of the protocols by the MODE bits in the GSMR. The HDLC controller uses
the same data structure as in all other modes. This data structure supports multibuffer oper-
ation and address comparisons.
7-174
FLAG
$7E
RECOGNIZES ONE 16-BIT ADDRESS (HADDR1) AND
ADDRESS
THE 16-BIT BROADCAST ADDRESS (HADDR2).
HADDR1
HADDR2
HADDR3
HADDR4
For 8-bit addresses, mask out (clear) the eight high-order bits in
the HMASK register.
The eight low-order bits of HMASK and HADDRx should contain
the address byte that immediately follows the opening flag. Ex-
ample: To recognize a frame that begins $7E (Flag), $68, $AA,
using 16-bit address recognition, HADDRx should contain
$AA68, and HMASK should contain $FFFF (see Figure 7-51).
The user should provide enough empty Rx BDs to receive the
number of frames specified in RFTHR.
HMASK
$68
16-BIT ADDRESS RECOGNITION
Figure 7-51. HDLC Address Recognition Example
ADDRESS
$AA
Freescale Semiconductor, Inc.
$FFFF
$FFFF
$AA68
$AA68
$AA68
For More Information On This Product,
CONTROL
MC68360 USER’S MANUAL
$44
Go to: www.freescale.com
NOTE
NOTE
ETC.
FLAG
$7E
RECOGNIZES A SINGLE 8-BIT ADDRESS (HADDR1).
HADDR2
HADDR3
HADDR4
HADDR1
HMASK
8-BIT ADDRESS RECOGNITION
ADDRESS
$55
$XX55
$XX55
$XX55
$XX55
$00FF
CONTROL
$44
ETC.