MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 262

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

System Integration Module (SIM60)
The SyncCLK must always be at least 2 the desired serial clock rate, and at least 2.5 the
desired serial clock rate if the time slot assigner (TSA) in the SI is used. See 7.8 Serial Inter-
face with Time Slot Assigner for more information on how to select an appropriate frequency
for the SyncCLK.
6.5.5.5 SIMCLK. SIMCLK is supplied to the SIM60 module. SIMCLK defaults to VCO/2 = 25
MHz (assuming a 25-MHz system frequency). The SIMCLK is the same as the general sys-
tem clock when slow-go mode is programmed in the CDVCR, but can operate differently
from the general system clock when the LPSTOP instruction is executed. The SIMCLK is
controlled in the PLLCR.
During the LPSTOP instruction, the PLL can be left enabled or can be disabled to conserve
power. This option is determined by the STSIM bit in PLLCR. If the PLL is disabled, the SIM-
CLK is either the EXTAL/2 or the EXTAL/128/2 frequency, depending on the divide-by-128
option.
6.5.5.6 CLKO1. CLKO1 is the same as the general system clock frequency. CLKO1
defaults to VCO/2 = 25 MHz (assuming a 25-MHz system frequency). CLKO1 can drive full
strength, 2/3 strength, 1/3 strength, or be disabled. This option is controlled in the CLKOCR.
Disabling or decreasing the strength of CLKO1 can reduce power consumption, noise, and
electromagnetic interference on the printed circuit board.
During the LPSTOP instruction, the PLL can be left enabled or can be disabled to conserve
power. This option is determined by the STSIM bit in PLLCR. If the PLL is disabled, CLKO1
is either the EXTAL/2 or EXTAL/128/2 frequency, depending on the divide-by-128 option.
6.5.5.7 CLKO2. CLKO2 is 2 general system clock frequency in normal operation. The
CLKO2 VCO normally equals 50 MHz (assuming a 25-MHz system frequency). CLKO2 can
drive full strength, 2/3 strength, 1/3 strength, or be disabled. This option is controlled in the
CLKOCR. Disabling or decreasing the strength of CLKO2 can reduce power consumption,
noise, and electromagnetic interference on the printed circuit board.
6-18
Since SyncCLK does not clock very much logic on the QUICC,
SyncCLK is normally left at its full frequency (25 MHz). However,
to temporarily lower the value of SyncCLK during an application
to save more power, SyncCLK must remain at its highest fre-
quency (e.g., 25 MHz) until the general system clock is reduced.
Only then can SyncCLK be lowered, and it must never be low-
ered to a frequency less than the general system clock frequen-
cy.
The SIMCLK is always the same frequency as CLKO1.
CLKO1 is always the same frequency as the SIMCLK.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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