MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 164
![IC MPU QUICC 32BIT 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68EN360ZQ25VL
Manufacturer Part Number
MC68EN360ZQ25VL
Description
IC MPU QUICC 32BIT 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360ZQ25VL.pdf
(962 pages)
Specifications of MC68EN360ZQ25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360ZQ25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360ZQ25VL PDF datasheet #4
- Current page: 164 of 962
- Download datasheet (4Mb)
CPU32+
5.3.3.5 SHIFT AND ROTATE INSTRUCTIONS. The arithmetic shift instructions, ASR and
ASL, and logical shift instructions, LSR and LSL, provide shift operations in both directions.
The ROR, ROL, ROXR, and ROXL instructions perform rotate (circular shift) operations,
with and without the extend bit. All shift and rotate operations can be performed on either
registers or memory.
Register shift and rotate operations shift all operand sizes. The shift count may be specified
in the instruction operation word (to shift from 1 to 8 places) or in a register (modulo 64 shift
count).
Memory shift and rotate operations shift word-length operands one bit position only. The
SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate
instructions is enhanced so that use of the ROR and ROL instructions with a shift count of
eight allows fast byte swapping. Table 5-7 is a summary of the shift and rotate operations.
5-22
Instruction
EORI
ANDI
EOR
AND
NOT
TST
ORI
OR
# data
# data
# data
Operand
Dn, ea
Dn, ea
Dn, ea
Syntax
ea , Dn
ea , Dn
ea
ea
Freescale Semiconductor, Inc.
For More Information On This Product,
ea
ea
ea
Table 5-6. Logic Operations
MC68360 USER’S MANUAL
Go to: www.freescale.com
Operand
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
Size
Source
Immediate Data
Source
Immediate Data
Destination
Source V Destination
Immediate Data V Destination
Source – 0, to set condition codes
Destination
Destination
Destination
Destination
Destination
Operation
Destination
Destination
Destination
Destination
Destination
Destination
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