MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 167

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

To specify conditions for change in program control, condition codes must be substituted for
the letters "cc" in conditional program control opcodes. Condition test mnemonics are given
below. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes.
5.3.3.9 SYSTEM CONTROL INSTRUCTIONS. Privileged instructions, trapping instruc-
tions, and instructions that use or modify the CCR provide system control operations. All of
these instructions cause the processor to flush the instruction pipeline. Table 5-11 summa-
rizes the instructions. The preceding list of condition tests also applies to the TRAPcc
instruction. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes.
—CC — Carry clear
—CS — Carry set
—EQ — Equal
—F
—GE — Greater or equal
—GT — Greater than
—HI
—LE — Less or equal
—*Not applicable to the Bcc instruction
Instruction
DBcc
NOP
BRA
BSR
JMP
RTD
RTR
RTS
JSR
Bcc
Scc
— False*
— High
Dn label
Operand
Syntax
none
none
none
label
label
label
Table 5-10. Program Control Operations
Freescale Semiconductor, Inc.
# d
ea
ea
ea
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Operand
8, 16, 32
8, 16, 32
8, 16, 32
none
none
none
none
none
Size
16
16
8
Unconditional
Conditional
Returns
If condition true, then PC + d
If condition false, then Dn – 1
If condition true, then destination bits are set to 1;
PC + d
SP – 4
Destination
SP – 4
PC + 2
(SP)
(SP)
(SP)
if Dn
else destination bits are cleared to 0
PC; SP + 4 + d
CCR; SP + 2
PC; SP + 4
– 1), then PC + d
SP; PC
SP; PC
PC
PC
LS —
LT —
MI —
NE —
PL —
T
VC —
VS —
PC
—
(SP); PC + d
(SP); destination
Operation
SP
SP; (SP)
Low or same
Less than
Minus
Not equal
Plus
True
Overflow clear
Overflow set
SP
PC
PC
PC;
PC; SP + 4
PC
PC
CPU32+
SP