MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 331

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

CH NUM—Channel Number
FLG—Command Semaphore Flag
GRACEFUL STOP TX. This command stops the transmission from this channel as soon
as the current frame has been fully transmitted from the transmit FIFO. Transmission will
proceed once the RESTART command is issued and the R-bit is set in the next transmit
buffer descriptor.
RESTART TX. When the STOP TX command has been issued, this command can be
used to restart the transmission at the current buffer descriptor.
CLOSE RX BD. This command causes the receiver to simply close the current receive
buffer descriptor, making the receive buffer immediately available for manipulation by the
user. Reception continues normally using the next available buffer descriptor. This com-
mand may be used to access the data buffer without waiting until the data buffer is com-
pletely filled by the SCC SET TIMER. This command activates, deactivates, or
reconfigures one of the 16 timers in the RISC timer table.
SET GROUP ADDRESS. This command sets a bit in the hash table for the Ethernet log-
ical group address recognition function.
GCI ABORT REQUEST. The GCI receiver sends an abort request on the E-bit.
GCI TIMEOUT. The GCI performs the timeout function.
RESET BCS. This command is used in BISYNC mode to reset the block check sequence
calculation.
Undefined (U). Reserved for use by Motorola-supplied RAM microcodes.
These bits are set by the host to define the specific sub-block on which the command is
to operate. Some sub-blocks share channel number encodings if their commands are mu-
tually exclusive.
The bit is set by the host and cleared by the CP.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SCC1
SCC2
SPI/RISC Timers
SCC3
SMC1/IDMA1
SCC4
SMC2/IDMA2
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Command Set