MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 163

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

5.3.3.4 LOGIC INSTRUCTIONS. The logical operation instructions (AND, OR, EOR, and
NOT) perform logical operations with all sizes of integer data operands. A similar set of
immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes
of immediate data. The test (TST) instruction arithmetically compares the operand with zero,
placing the result in the CCR. Table 5-6 summarizes the logical operations.
TBLSN/TBLUN
DIVSL/DIVUL
MULS/MULU
TBLS/TBLU
Instruction
DIVS/DIVU
CMPM
ADDQ
CMPA
ADDA
ADDX
CMP2
NEGX
SUBA
SUBQ
SUBX
EXTB
CMPI
ADDI
SUBI
CMP
NEG
ADD
CLR
SUB
EXT
– (An), – (An)
(An) +, (An) +
– (An), – (An)
Dym:Dyn, Dn
Dym:Dyn, Dn
# data
# data
# data
# data
# data
ea , Dr:Dq
ea , Dr:Dq
ea , Dh:Dl
Operand
Dn, ea
Dn, ea
Syntax
Dn, Dn
Dn, Dn
ea , Dn
ea , Dn
ea , Rn
ea , Dn
ea , Dq
ea , Dn
ea , Dn
ea , Dn
ea , Dn
ea , An
ea , An
ea , An
ea , Dl
Table 5-5. Integer Arithmetic Operations
Freescale Semiconductor, Inc.
Dn
Dn
Dn
ea
ea
ea
For More Information On This Product,
ea
ea
ea
ea
ea
MC68360 USER’S MANUAL
32/16
64/32
32/32
Go to: www.freescale.com
16
32
32
32/32
Operand
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
8
8
16, 32
16, 32
16, 32
Size
16
32
32
16
32
16:16
32:32
32:32
32
32
32
32
64
Source + Destination
Source + Destination
Immediate Data + Destination
Immediate Data + Destination
Source + Destination + X
(Destination – Source), CCR shows results
(Destination – Source), CCR shows results
(Destination – Immediate Data), CCR shows results
(Destination – Source), CCR shows results
Lower bound Rn Upper Bound, CCR shows results
Destination/Source
signed)
Sign Extended Destination
Sign Extended Destination
Source
signed)
0 – Destination
0 – Destination – X
Destination – Source
Destination – Source
Destination – Immediate Data
Destination – Immediate Data
Destination – Source – X
Dyn – Dym
(Temp
(Dym
Dyn – Dym
(Temp
Dym + Temp
Destination
256) + Temp
Dn [7:0])
Dn [7:0]) / 256
Destination
Temp
Temp
Dn
Destination
Temp
Operation
Destination (signed or un-
Destination
Dn
Destination (signed or un-
Destination
Destination
Destination
Destination
Temp
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
CPU32+