MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 8
![IC MPU QUICC 32BIT 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68EN360ZQ25VL
Manufacturer Part Number
MC68EN360ZQ25VL
Description
IC MPU QUICC 32BIT 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360ZQ25VL.pdf
(962 pages)
Specifications of MC68EN360ZQ25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360ZQ25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360ZQ25VL PDF datasheet #4
- Current page: 8 of 962
- Download datasheet (4Mb)
Table of Contents
Paragraph
Number
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.6.1
4.6.6.2
4.6.7
4.6.8
4.7
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.2
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.3.4
5.3.3.5
5.3.3.6
5.3.3.7
5.3.3.8
5.3.3.9
5.3.3.10
5.3.4
5.3.4.1
5.3.4.2
iv
Bus Arbitration .......................................................................................4-49
Bus Request ..........................................................................................4-52
Bus Grant...............................................................................................4-53
Bus Grant Acknowledge ........................................................................4-53
Bus Arbitration Control...........................................................................4-54
Slave (Disable CPU32+) Mode Bus Arbitration .....................................4-55
Slave (Disable CPU32+) Mode Bus Exceptions ....................................4-59
HALT......................................................................................................4-59
RETRY...................................................................................................4-59
Internal Accesses...................................................................................4-59
Show Cycles ..........................................................................................4-62
Reset Operation.....................................................................................4-63
Overview ..................................................................................................5-1
Features...................................................................................................5-2
Loop Mode Instruction Execution.............................................................5-3
Vector Base Register ...............................................................................5-4
Exception Handling ..................................................................................5-4
Addressing Modes ...................................................................................5-5
Architecture Summary .............................................................................5-5
Programming Model.................................................................................5-6
Registers..................................................................................................5-7
Instruction Set ..........................................................................................5-8
M68000 Family Compatibility.................................................................5-10
New Instructions. ...................................................................................5-10
Low-Power Stop (LPSTOP). ..................................................................5-10
Table Lookup and Interpolate (TBL). .....................................................5-10
Unimplemented Instructions. .................................................................5-10
Instruction Format and Notation.............................................................5-10
Instruction Summary ..............................................................................5-13
Condition Code Register........................................................................5-17
Data Movement Instructions ..................................................................5-19
Integer Arithmetic Operations ................................................................5-19
Logic Instructions. ..................................................................................5-21
Shift and Rotate Instructions..................................................................5-22
Bit Manipulation Instructions ..................................................................5-23
Binary-Coded Decimal (BCD) Instructions.............................................5-24
Program Control Instructions .................................................................5-24
System Control Instructions ...................................................................5-25
Condition Tests ......................................................................................5-26
Using the TBL Instructions.....................................................................5-27
Table Example 1: Standard Usage ........................................................5-28
Table Example 2: Compressed Table....................................................5-29
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Section 5
CPU32+
Title
Number
Page
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