MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 739

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

than it is to the system integration block on the MC68302. The QUICC communications fea-
tures, however, are very similar to those of the MC68302.
9.3.3 Notes About Porting
Although the following paragraphs show how to port MC68302 functions to the QUICC, it
should not be assumed that the port operation will provide a complete initialization of the
QUICC. The QUICC contains features not available on the MC68302 that may require addi-
tional initialization. For instance, the QUICC contains an on-chip PLL to generate a high-
speed system clock frequency from a low-speed crystal, such as a 32-kHz crystal. Since this
feature is not available on the MC68302, it is not mentioned in this discussion. Refer to 9.2
How to take A QUICC Software Test-Drive as a guide to complete QUICC initialization.
Although the QUICC was designed to allow a convenient upgrade path from the MC68302,
this discussion does not guarantee that every MC68302 operation can be exactly and pre-
cisely duplicated on the QUICC. For instance, when using the serial channels, the time
between setting the ready bit of a buffer descriptor and the assertion of the RTS pin may not
be the same on the QUICC as the MC68302. Also, although the MC68302 hardware watch-
dog can be implemented in the QUICC bus monitor, the MC68302 maximum timeout is 16K
clocks; whereas, the QUICC maximum timeout period is 1K clocks (before BERR is
asserted on the system bus).
The QUICC offers features that simplify what would otherwise be a more code-intensive pro-
cess. For specific examples, see the INIT TX AND RX PARAMETERS, the GRACEFUL
STOP TRANSMIT, and the CLOSE BD commands. The user can do a direct port using the
old commands and techniques; however, the new commands may be used in many
instances to simplify the application process.
Additionally, the most direct port to the QUICC will not necessarily take advantage of a num-
ber of new QUICC features. For specific examples, see the dynamic allocation of SCC inter-
rupt levels and the buffer descriptor capability of the independent DMA (IDMA) channels.
Some comments will be made about these features where appropriate.
9.3.4 How To Port MC68302 Functions
The following paragraphs detail the different MC68302 functions and how/where to imple-
ment them on the QUICC. The MC68302 functions are listed in ascending order in the
MC68302 memory map.
9.3.4.1 SYSTEM CONFIGURATION REGISTERS. The following paragraphs describe the
MC68302 configuration registers.
9.3.4.1.1 Base Address Register (BAR). This register is most closely related to the MBAR
on the QUICC:
The base address field is configured in the BA bits of the MBAR. Be sure to allow 8 Kbytes
in the memory map of the QUICC system at this address. Also, the V-bit of MBAR must
be set before the contents are valid.
The CFC bit and FC2–FC0 bits may be duplicated by setting all but one of the AS7–AS0
bits in the MBAR. Note that the MBAR offers many more options since multiple AS bits
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
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