MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 615

IC MPU QUICC 32BIT 357-PBGA

MC68EN360ZQ25VL

Manufacturer Part Number
MC68EN360ZQ25VL
Description
IC MPU QUICC 32BIT 357-PBGA
Manufacturer
Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EN360ZQ25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
7.11.9 SMC Interrupt Handling
The following list describes what would normally occur within an interrupt handler for the
SMC:
7.11.10 SMC as a Transparent Controller
The following paragraphs describe using the SMC as a transparent controller.
7.11.10.1 SMC TRANSPARENT CONTROLLER KEY FEATURES. The SMC transparent
controller contains the following key features:
14. Write $FF to the SMCE to clear any previous events.
15. Write $17 to the SMCM to enable all possible SMC interrupts.
16. Write $00000010 to the CIMR to allow SMC1 to generate a system interrupt. (The
17. Write $4820 to SMCMR to configure normal operation (not loopback), 8-bit
18. Write $4823 to SMCMR to enable the SMC transmitter and receiver. This
1. Once an interrupt occurs, read the SMCE to see which sources have caused inter-
2. Process the Tx BD to reuse it if the TX bit was set in SMCE. Extract data from the Rx
3. Clear the SMC1 bit in the CISR.
4. Execute the RTE instruction.
• Flexible Data Buffers
• May Be Used To Connect to a TDM Bus using the TSA in the SI
• May Transmit and Receive Transparently on Its Own Set of Pins using a Sync Pin To
• Programmable Character Length (4–16)
• Reverse Data Mode
Synchronize the Beginning of Transmission and Reception to an External Event
and contains five 8-bit characters. Write $B000 to Tx_BD_Status. Write $0005 to
Tx_BD_Length. Write $00002000 to Tx_BD_Pointer.
CICR should also be initialized.)
characters, no parity, 1 stop bit. Notice that the transmitter and receiver have
not been enabled yet.
additional write ensures that the TEN and REN bits will be enabled last.
rupts. The SMCE bits would normally be cleared at this time.
BD if the RX bit was set in SMCE. To transmit another buffer, simply set the Tx BD R-
bit.
After 5 bytes have been transmitted, the Tx BD is closed. Addi-
tionally, the receive buffer is closed after 16 bytes have been re-
ceived. Any additional receive data beyond 16 bytes will cause
a busy (out-of-buffers) condition since only one Rx BD was pre-
pared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Serial Management Controllers (SMCs)

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