TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 106

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7.6
Exception/Interrupt-Related Registers
31-30
29
28-7
6-0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
7.6.2.14
Bit
−
TBLBASE
TBLOFF
−
Bit Symbol
TBLOFF
Vector Table Offset Register
31
23
15
0
0
0
7
0
-
R
R/W
R/W
R
Type
30
22
14
0
0
0
6
0
-
-
Read as 0.
Table base
The vector table is in:
0: Code space
1: SRAM space
Offset value
Set the offset value from the top of the space specified in TBLBASE.
The offset must be aligned based on the number of exceptions in the table.This means that the minimum
alignment is 32 words that you can use for up to 16 interrupts.For more interrupts, you must adjust the alignment
by rounding up to the next power of two.
Read as 0.
TBLBASE
29
21
13
0
0
0
5
0
-
Page 86
28
20
12
0
0
0
4
0
-
TBLOFF
TBLOFF
27
19
11
Function
0
0
0
3
0
-
TBLOFF
26
18
10
0
0
0
2
0
-
TMPM333FDFG/FYFG/FWFG
25
17
0
0
9
0
1
0
-
24
16
0
0
8
0
0
0
-