TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 88

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7.5
Interrupts
7.5.2.2
Return to preceding program
ISR execution
Processing
unexpected interrupt on the way.
Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then enable the interrupt
by the CPU.
interrupt. First, configure the precondition. Secondly, clear the data related to the interrupt in the clock gen-
erator and then enable the interrupt.
(1)
(2)
When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any
Initiating an interrupt or changing its configuration must be implemented in the following order basically.
To configure the clock generator, you must follow the order indicated here not to cause any unexpected
The following sections are listed in the order of interrupt handling and describe how to configure them.
Preparation
Register. All interrupts and exceptions other than non-maskable interrupts and hard faults can be masked.
NVIC register.
Interrupt mask register
PRIMASK
1. Disabling interrupt by CPU
2. CPU registers setting
3. Preconfiguration (1) (Interrupt from external pin)
4. Preconfiguration (2) (Interrupt from peripheral function)
5. Preconfiguration (3) (Interrupt Set-Pending Register)
6. Configuring the clock generator
7. Enabling interrupt by CPU
Note 1: PRIMASK register cannot be modified by the user access level.
Note 2: If a fault causes when "1" is set to the PRIMASK register, it is treated as a hard fault.
To make the CPU for not accepting any interrupt, write "1" to the corresponding bit of the PRIMASK
Use "MSR" instruction to set this register.
You can assign a priority level by writing to <PRI_n> field in an Interrupt Priority Register of the
Disabling interrupt by CPU
CPU registers setting
Program for the ISR.
Clear the interrupt source if needed.
Configure to return to the preceding program of the ISR.
←
"1" (interrupt disabled)
Page 68
Details
TMPM333FDFG/FYFG/FWFG
Service Routine (ISR)"
"7.5.2.6 Interrupt
See