TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 301

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.5.2
11.5.3
11.5.4
11.5.5
clock for acknowledgment signal. In slave mode, the clock for acknowledgement signals is counted. In transmitter
mode, the SBI releases the SDAx pin during clock cycle to receive acknowledgement signals from the receiver.
In receiver mode, the SBI pulls the SDAx pin to the "Low" level during the clock cycle and generates acknowl-
edgement signals. Also in slave mode, if a general-call address is received, the SBI pulls the SDAx pin to the
"Low" level during the clock cycle and generates acknowledgement signals.
does not generate clock for acknowledgement signals. In slave mode, the clock for acknowledgement signals is
counted.
ferred in a packet of eight bits. At other times, <BC[2:0]> keeps a previously programmed value.
then the SBI recognizes a slave address transmitted by the master device and receives data in the addressing
format.
the case of free data format, a slave address and a direction bit are not recognized; they are recognized as data
immediately after generation of the start condition.
serial bus interface pins are at "High" level before setting <SBIM[1:0]> to "10". Also, ensure that the bus is free
before switching the operating mode to the port mode.
Setting SBIxCR1<ACK> to "1" selects the acknowledge mode.When operating as a master, the SBI adds one
By setting <ACK> to "0", the non-acknowledgment mode is activated. When operating as a master, the SBI
SBIxCR1<BC[2:0]> specifies the number of bits of the next data to be transmitted or received.
Under the start condition, <BC[2:0]> is set to "000", causing a slave address and the direction bit to be trans-
Setting "0" to SBIxI2CAR<ALS> and a slave address in SBIxI2CAR<SA[6:0]> sets addressing format, and
If <ALS> is set to "1", the SBI does not recognize a slave address and receives data in the free data format. In
The setting of SBIxCR2<SBIM[1:0]> controls the operating mode. To operate in I2C mode, ensure that the
the "High" level. However, Master B still keeps the SCL bus line at the "Low" level, and Master A stops
counting of its "High" level period counting.After Master A detects that Master B brings its internal SCL
output to the "High" level and brings the SCL bus line to the "High" level at the point c, it starts counting of
its "High" level period.
SCL bus line becomes "Low".
master with the longest "Low" level period among those connected to the bus.
Setting the Acknowledgement Mode
Setting the Number of Bits per Transfer
Slave Addressing and Address Recognition Mode
Operating mode
Master A completes counting of its "Low" level period at the point b, and brings its internal SCL output to
After that Master finishes counting the "High" level period, the Master pulls the SCL pin to "Low" and the
This way, the clock on the bus is determined by the master with the shortest "High" level period and the
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TMPM333FDFG/FYFG/FWFG