TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 258

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.7
Clock Control
Transfer rate =
Baud rate calculation
・ If timer output is used
Clock frequency selected by CGSYSCR<PRCK[1:0]>
Table 10-9 Example of UART Mode Baud Rate (Using the Timer Output)
inverts when the value of the counter and that of TBxRG0 match. The SIOCLK clock frequency
is "Setting value of TBxRG0 × 2".
clock settings.
・ fc = 32MHz / 9.8304MHz / 8MHz
・ fgear = 32MHz / 9.8304MHz / 8MHz (CGSYSCR<GEAR[2:0]> = "000" : fc selected)
・ ΦT0 = 16MHz / 4.9152MHz / 4MHz (CGSYSCR<PRCK[2:0]> = "001" : 2 division
・ Timer count clock = 4MHz / 1.2287MHz / 1MHz (TBxMOD<TBCLK[1:0]> = "01" :
To enable the timer output, the following condition must be set: a timer flip-flop output
Baud rates can be obtained by using the following formula.
Table 10-9 shows the examples of baud rates when the timer output is used with the following
TBxRG0 setting
ratio)
ΦT1 selected)
0x000A
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0008
0x0010
0x0014
(TBxRG0 × 2) × 2 × 16
O ne clock cycle is a period that the tim er flip-flop
is inv erted twice.
32MHz
15.625
31.25
62.5
12.5
250
125
Page 238
50
25
-
-
In the case the tim er prescaler clock Φ T 1
(2div ition ratio) is selected.
9.8304MHz
15.36
76.8
38.4
25.6
19.2
12.8
7.68
3.84
9.6
4.8
fc
15.625
8MHz
31.25
3.125
Unit：kbps
62.5
12.5
6.25
-
-
-
-
TMPM333FDFG/FYFG/FWFG