TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 261

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.10.2
10.10.3
the parity received.
transmit shift register with no data in the tarnsmit buffer.
the center. Regardless of the stop bit length settings in the SCxMOD2<SBLEN>register, the stop bit status is
determined by only 1.
In the I/O interface with SCLK output mode, the SCLK output stops upon setting the flag.
This flag indicates a parity error in the UART mode and an under-run error in the I/O interface mode.
In the UART mode, <PERR> is set to "1" when the parity generated from the received data is different from
In the I/O interface mode, <PERR> is set to "1" under the following conditions when a double buffer is enabled.
In the SCLK input mode, <PERR> is set to "1" when the SCLK is input after completing data output of the
In the SCLK output mode, <PERR> is set to "1" after completing output of all data and the SCLK output stops.
A framing error is generated if the corresponding stop bit is determined to be "0" by sampling the bit at around
This bit is fixed to "0" in the I/O interface mode.
Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and clear the
Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and clear the
PERR Flag
FERR Flag
overrun flag.
under-run flag.
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TMPM333FDFG/FYFG/FWFG