TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 272

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.14
Interrupt/Error Generation Timing
10.14.2
10.14.2.1
10.14.2.2
Figure 10-11 shows the data flow of transmit operation and the route of read.
are given as follows.
SCxTFC<TFIS> setting are established.
TX interrupts
Table 10-13 Transmit Interrupt conditions in use of FIFO
TX interrupts are generated at the time depends on the transfer mode and the buffer configurations, which
In use of FIFO, transmit interrupt is generated on the condition that the fllowing either operation and
Interrupt conditions are decided by the SCxTFC<TFIS> settings as described in Table 10-13.
Note:If double buffer is enabled, a interrupt is also generated when the data is moved from the buffer to the
SCxTFC<TFIS>
Configurations
Double Buffer
Single Buffer / Double Buffer
Single Buffer
FIFO
・ Transmittion completion of all bits of one frame.
・ Writing FIFO
Figure 10-11 Transmit Buffer/FIFO Configuration Diagram
shift register by writing to the buffer.
Buffer
"0"
"1"
"The fill level of FIFO" is equal to "the fill level of FIFO interruption generation."
"The fill level of FIFO" is smaller than or equal to "the fill level of FIFO intrruption generation."
Just before the stop bit is sent
When a data is moved from the transmit buffet to the transmit shift register.
UART modes
Page 252
Interrupt conditions
Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
IO interface modes
TMPM333FDFG/FYFG/FWFG