TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 414

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15.2
Operation Mode
15.2.10.2
See Table 15-7 for the transfer format of this command.
Show Flash Memory SUM Command
9. The 23rd and 24th bytes, transmitted from the controller to the target board, indicate the number
10. The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the checksum value,
11. The 26th byte, transmitted from the target board to the controller, is an acknowledge response to
12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the TMPM333FDFG/
13. The (m+1) th byte is a checksum value. To calculate the checksum value, add the 27th to mth
14. The (m+2) th byte is a acknowledge response to the 27th to (m+1) th bytes. First, the RAM Transfer
15. If the (m+2) th byte was a normal acknowledge response, a branch is made to the
1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command.
of bytes that will be transferred from the controller to be stored in the RAM. The 23rd byte cor-
responds to bits 15.8 of the number of bytes to be transferred, and the 24th byte corresponds to
bits 7.0 of the number of bytes.
add all these bytes together, drop the carries and take the two’s complement of the total sum.
Transmit this checksum value from the controller to the target board. The checksum calculation
is described in details in a later section "Checksum Calculation".
the 19th to 25th bytes of data. First, the RAM Transfer routine checks for a receive error in the
19th to 25th bytes. If there was a receive error, the RAM Transfer routine sends back 0x18 and
returns to the command wait state (i.e., the 3rd byte) again. In this case, the upper four bits of the
acknowledge response are the same as those of the previously issued command (i.e., 1). When the
SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive
error.
Adding the series of the 19th to 25th bytes must result in 0x00 (with the carry dropped). If it is
not 0x00, one or more bytes of data has been corrupted. In case of a checksum error, the RAM
Transfer routine sends back 0x11 to the controller and returns to the state in which it waits for a
command (i.e., the 3rd byte) again.
knowledge response (0x10) to the controller.
FYFG/FWFG. Storage begins at the address specified by the 19th.22nd bytes and continues for
the number of bytes specified by the 23rd.24th bytes.
bytes together, drop the carries and take the two’s complement of the total sum. Transmit this
checksum value from the controller to the target board. The checksum calculation is described in
details in a later section "Checksum Calculation".
routine checks for a receive error in the 27th to (m+1) th bytes. If there was a receive error, the
RAM Transfer routine sends back 0x18 (bit 3) and returns to the state in which it waits for a
command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response
are the same as those of the previously issued command (i.e., 1). When the SIO0 is configured for
I/O Interface mode, the RAM Transfer routine does not check for a receive error.
Adding the series of the 27th to (m+1) th bytes must result in 0x00 (with the carry dropped). If it
is not 0x00, one or more bytes of data has been corrupted. In case of a checksum error, the RAM
Transfer routine sends back 0x11 (bit 0) to the controller and returns to the command wait state
(i.e., the 3rd byte) again. When the above checks have been successful, the RAM Transfer routine
returns a normal acknowledge response (0x10) to the controller.
address specified by the 19th to 22nd bytes.
・ The RAM storage start address must be within the range of 0x2000_0400 to the end address
Next, the RAM Transfer routine performs the checksum operation to ensure data integrity.
When the above checks have been successful, the RAM Transfer routine returns a normal ac-
Next, the RAM Transfer routine performs the checksum operation to ensure data integrity.
of RAM.
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TMPM333FDFG/FYFG/FWFG