TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 314
TMPM333FDFG
Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Specifications of TMPM333FDFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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11.6
Data Transfer Procedure in the I2C Bus ModeI2C
SCL(Bus)
SCL pin
SDA pin
<LRB>
<BB>
<PIN>
SBIxCR2
if SBIxSR<BB> ≠ 0
Then
if SBIxSR<LRB> ≠ 1
Then
4.7 μs Wait
SBIxCR1
SBIxDBR
SBIxCR2
Note:X; Don’t care
restart becomes "1", the rising edge of the SCL line is not detected even <LBR>= "1" is confirmed
by following the restart procedure. To check the status of the SCL line, read the port.
←
←
←
←
Figure 11-14 Timing Chart of Generating a Restart
7
0
X
X
1
"0"→<MST>
"0"→<TRX>
"0"→<BB>
"1"→<PIN>
6
0
X
X
1
9
5
0
X
X
1
4
1
1
X
1
3
1
0
X
1
2
0
X
X
0
1
0
X
X
0
Page 294
0
0
X
X
0
"1"→<MST>
"1"→<TRX>
"1"→<BB>
"1"→<PIN>
Releases the bus.
Checks that the SCL pin is released.
Checks that no other device is pulling the SCL pin to the "Low".
Selects the acknowledgment mode.
Sets the desired slave address and direction.
Generates the start condition.
4.7 ms (min.)
TMPM333FDFG/FYFG/FWFG
Start condition
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