TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 151

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TMPM333FDFG

Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Datasheets

Specifications of TMPM333FDFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM333FDFG
Manufacturer:
Toshiba
Quantity:
10 000
8.2.7
Type
8.2.7.1
8.2.7.2
units of bits.
external interrupt input, and the 16-bit timer output.
input in the PGIE register.
is set to stop driving of pins during STOP mode.
Port G data register
Port G output control register
Port G function register 1
Reserved
Port G open drain control register
Port G pull-up control register
Port G input control register
Port G (PG0 to PG7)
The port G is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in
Besides the general-purpose port function, the port G performs the functions of the serial bus interface, the
Reset initializes all bits of the port G as general-purpose ports with input, output and pull-up disabled.
To use the external interrupt input for releasing STOP mode, select function in the PGFR register and enable
These settings enable the interrupt input even if the CGSTBYCR<DRVE> bit in the clock/mode control block
Note:In modes other than STOP mode, interrupt input is enabled regardless of the PGFR register setting if
Port G Circuit Type
Port G Register
Note:Access to the "reserved" areas is prohibited.
input is enabled in PGIE. Make sure to disable unused interrupts when programming the device.
T10
7
T13
6
Register name
T13
5
Page 131
T13
4
PGDATA
PGPUP
PGFR1
PGCR
PGOD
PGIE
-
T8
3
T13
2
Base Address = 0x4000_0180
TMPM333FDFG/FYFG/FWFG
Address (Base+)
0x002C
0x0000
0x0004
0x0008
0x0010
0x0028
0x0038
T13
1
T13
0

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