TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 107

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

31-16
15
14-11
10-8
7-3
2
1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
7.6.2.15
VECTKEY
(Write)/
VECTKEY-
STAT(Read)
ENDIANESS
−
PRIGROUP
−
SYSRESET
REQ
VECTCLR
ACTIVE
VECTRESET
Bit Symbol
ENDIANESS
Note 1: Little-endian is the default memory format for this product.
Note 2: When SYSRESETREQ is output, warm reset is performed on this product. <SYSRESETREQ> is
Application Interrupt and Reset Control Register
31
23
15
0
0
0
7
0
-
cleared by warm reset.
R/W
R/W
R
R/W
R
R/W
R/W
R/W
Type
30
22
14
0
0
0
6
0
Register key
[Write] Writing to this register requires 0x5FA in the <VECTKEY> field.
[Read] Read as 0xFA05.
Endianness bit:(Note1)
1: big endian
0: little endian
Read as 0.
Interrupt priority grouping
000: seven bits of pre-emption priority, one bit of subpriority
001: six bits of pre-emption priority, two bits of subpriority
010: five bits of pre-emption priority, three bits of subpriority
011: four bits of pre-emption priority, four bits of subpriority
100: three bits of pre-emption priority, five bits of subpriority
101: two bits of pre-emption priority, six bits of subpriority
110: one bit of pre-emption priority, seven bits of subpriority
111: no pre-emption priority, eight bits of subpriority
The bit configuration to split the interrupt priority register <PRI_n> into pre-emption priority and sub priority.
Read as 0.
System Reset Request.
1=CPU outputs a SYSRESETREQ signal. (note2)
Clear active vector bit
1: clear all state information for active NMI, fault, and interrupts
0: do not clear.
This bit self-clears.
It is the responsibility of the application to reinitialize the stack.
System Reset bit
1: reset system
0: do not reset system
Resets the system, with the exception of debug components (FPB, DWT and ITM) by setting "1" and this bit is
also zero cleared.
-
-
29
21
13
0
0
0
5
0
-
-
VECTKEY/VECTKEYSTAT
VECTKEY/VECTKEYSTAT
Page 87
28
20
12
0
0
0
4
0
-
-
27
19
11
Function
0
0
0
3
0
-
-
SYSRESET
REQ
26
18
10
0
0
0
2
0
TMPM333FDFG/FYFG/FWFG
PRIGROUP
VECTCLR
ACTIVE
25
17
0
0
9
0
1
0
VECTRESET
24
16
0
0
8
0
0
0