TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 256

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.7
Clock Control
10.7.2.2
by setting SCxMOD0<SC>.
Table 10-6 Clock Selection in I/O Interface Mode
(1)
A clock can be selected by setting the modes and the register.
Modes can be specified by setting the SCxMOD0<SM>.
The input clock in I/O interface mode is selected by setting SCxCR. The clock in UART mode is selected
I/O interface mode
Clock Selection Circuit
SCxMOD0<SM>
Table 10-6 shows clock selection in I/O interface mode.
To get the highest baud rate, the baud rate generator must be set as below.
To use SCLK input, the following conditions must be satisfied.
Mode
Note:When deciding clock settings, make sure that AC electrical character is satisfied.
Transfer Clock in I/O interface mode
・ Clock/mode control block settings
・ SIO settings (if double buffer is used)
・ SIO settings (if double buffer is not used)
・ If double buffer is used
・ If double buffer is not used
because 20MHz is divided by 2.
because 10MHz is divided by 2.
-
-
-
-
-
-
-
1 division ratio can be selected if double buffer is used. In this case, baud rate is 10Mbps
2 division ratio is the highest if double buffer is not used. In this case, baud rate is 5Mbps
- SCLK cycle > 6/fsys
The highest baud rate is less than 40 ÷ 6 = 6.66 Mbps.
- SCLK cycle > 8/fsys
fc = 40MHz
fgear = 40MHz (CGSYSCR<GEAR[2:0]> = "000" : fc selected)
ΦT0 = 40MHz (CGSYSCR<PRCK[2:0]> = "000" : 1 division ratio)
Clock (SCxBRCR<BRCK[1:0]> = "00" : ΦT1 selected) = 20MHz
Divided clock frequency (SCxBRCR<BRS[3:0]> = "0001" : 1 division ratio) = 20MHz
Clock (SCxBRCR<BRCK[1:0]> = "00" : ΦT1 selected) = 20MHz
Divided clock frequency (SCxBRCR<BRS[3:0]> = "0010" : 2 division ratio) = 10MHz
SCxCR<IOC>
SCLK output
Input/Output
SCLK input
selection
Page 236
(Fixed to the rising edge)
Clock edge selection
SCxCR<SCLKS>
Falling edge
Rising edge
Set to "0".
Divided by 2 of the baud rate gen-
SCLK input falling edge
SCLK input rising edge
erator output.
Clock of use
TMPM333FDFG/FYFG/FWFG