TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 52
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TMPM333FDFG
Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Specifications of TMPM333FDFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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5.2
Warm reset
5.2
5.2.1
5.2.2
Warm reset
frequency oscillator is providing stable oscillation.
12 system clocks.
function registers.
register and the FCSECBIT register are initialized by a only cold reset.
Reset period
After reset
As a precondition, ensure that the power supply voltage is within the operating range and the internal high-
To reset the TMPM333FDFG/FYFG/FWFG, assert the RESET signal (active low) for a minimum duration of
A warm reset initializes the majority of the Cortex-M3 processor core's system control registers and internal
The processor core's system debug components (FPB, DWT, ITM) register, the clock generator's CGRSTFLG
After reset, the PLL multiplication circuit is inactive and must be enabled in the CGPLLSEL register if needed.
When the reset exception handling is completed, the program branches to the reset interrupt service routine.
Note:The reset operation may alter the internal RAM state.
Page 32
TMPM333FDFG/FYFG/FWFG
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