TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 37

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

2. Processor Core
2.1
2.2
2.3
2.3.1
mation on the operations of this processor core, please refer to the "Cortex-M3 Technical Reference Manual" issued
by ARM Limited.This chapter describes the functions unique to the TX03 series that are not explained in that document.
processors" in the following URL:
following tables shows the configurable options in the TMPM333FDFG/FYFG/FWFG.
Information on the processor core
Configurable Options
Exceptions/ Interruptions
The TX03 series has a high-performance 32-bit processor core (the ARM Cortex-M3 processor core). For infor-
The following table shows the revision of the processor core in the TMPM333FDFG/FYFG/FWFG.
Refer to the detailed information about the CPU core and architecture, refer to the ARM manual "Cortex-M series
http://infocenter.arm.com/help/index.jsp
The Cortex-M3 core has optional blocks. The optional blocks of the revision r1p1 are ETM™ and MPU. The
Exceptions and interruptions are described in the following section.
TLINESNUM[4:0]> bit of NVIC register. In this product, if read <INTLINESNUM[4:0]> bit, "0y00001" is read
out.
Number of Interrupt Inputs
The number of interrupt inputs can optionally be defined from 1 to 240 in the Cortex-M3 core.
TMPM333FDFG/FYFG/FWFG has 46 interrupt inputs. The number of interrupt inputs is reflected in <IN-
Configurable Options
TMPM333FWFG
TMPM333FDFG
TMPM333FYFG
Product Name
MPU
ETM
Page 17
Not implementable
Implementation
Implementable
Core Revision
r1p1-00rel0
r1p1-01rel0
TMPM333FDFG/FYFG/FWFG